1. Field of the Invention
The present invention relates to an IC card and, more particularly, to an IC card which has, in addition to a semiconductor memory for storing the main data, a semiconductor memory for storing physical information concerning the card and format information concerning the data in the card.
2. Description of the Related Art
FIG. 4 shows an IC card of the type described above. The IC card has a 256K bit static random access memory (RAM) 1 serving as an area for storing main data, and a 64K bit electrically erasable programmable read-only memory (EEPROM) for storing physical information concerning the IC card, e.g., type and capacity of the memory, access time and so on, as well as format information concerning the data stored in the IC card. A mode control circuit 3 is connected to the static RAM 1 and the EEPROM 2. In addition, all the address signal lines A.sub.0 to A.sub.14 of an address BUS 5 are connected to the static RAM 1. Selected address signal lines A.sub.0 to A.sub.12 of the BUS are also connected to the EEPROM 2. Furthermore, a data BUS 7 including 8-bit data signal lines D.sub.0 to D.sub.7 is connected to the static RAM 1 and also to the EEPROM 2.
The mode control circuit 3 receives a card enable signal CE and a memory selection signal REG. A chip enable signal S.sub.1 of "L" level is delivered to the static RAM 1 when the card enable signal CE is "L" while the memory selection signal REG is "H" level. When both the card enable signal CE and the memory selection signal REG are "L" level, a chip enable signal S.sub.2 of "L" level is delivered to the EEPROM 2.
The operation of this IC card is as follows. When it is desired to use the static RAM 1, a terminal device which is not shown sets the card enable signal CE to "L" level and set the memory selection signal REG to "H" level. As a result, a chip enable signal S.sub.1 of "L" level is delivered from the mode control circuit 3 to the static RAM 1 so that the static RAM 1 becomes ready to operate. In this state, and address is selected through the address signal lines A.sub.0 to A.sub.14, and read control signal OE and write control signal WE are respectively set to "L" and "H" levels, so that data stored in the selected address of the RAM 1 appears on the data BUS 7. Conversely, when the read control signal OE and the write control signal WE are respectively set to "H" and "L" levels, data on the data BUS 7 are written in the selected address of the static RAM 1. The data in the static RAM 1 is lost when the power supply is turned off.
On the other hand, when the EEPRM 2 is to be used, both the card enable signal CE and the memory selection signal REG are set to "L" levels. As a result, a chip enable signal S.sub.2 of "L" level is delivered to the EEPROM 2 from the mode control circuit 3, thereby enabling the EEPROM 2 to operate. Reading and writing of data are conducted in the same manner as those in the case of the static RAM 1. The data in the EEPROM 2 is not lost even when the power supply is turned off.
When both the static RAM 1 and the EEPRM 2 are not to be used, the card enable signal CE is set to "H" level. In this case, both the chip enable signals S.sub.1 and S.sub.2 are set to "H" so that the static RAM 1 and the EEPROM 2 become inoperative.
In this known IC card, the EEPROM 2 can be accessed easily through a terminal device (not shown) as described above, so that a problem has been encountered that physical information concerning the card and stored in the EEPRM 2 may be rewritten accidentally or willfully.